In a note from Bernstein Research (via Barron's), analysts Mark Li and David Dai question the belief that Taiwan Semiconductor will close the chip manufacturing technology gap with Intel . The analysts note that the 10-nanometer manufacturing technology "won't generate significant revenue for TSMC until mid-2017," and that in order to catch up with what Intel is doing at 10-nanometers it will have to perform "the most aggressive shrink" in history.
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Let's take a closer look at what exactly Bernstein's analysts are talking about.
Taiwan Semiconductor's claims
Taiwan Semiconductor's Elizabeth Sun claimed in an interview with EETimes that the company's 10-nanometer technology would match what Intel brings with its 10-nanometer technology. The point that the Bernstein analysts are trying to make is that this may not actually be the case given how big of a leap that would require.
Let's talk density
Consider that a common metric (used by various chip manufacturers in scientific papers) used to measure the density of a given technology is gate pitch multiplied by minimum metal pitch. Taiwan Semiconductor's 16-nanometer technology features a gate pitch of 90-nanometers and a minimum metal pitch of 64-nanometers. Those numbers for Intel's 14-nanometer technology are 70-nanometers and 52-nanometers respectively.
Multiplying them out gets us 5760 for the TSMC 16-nanometer technology and 3640 for the Intel 14-nanometer technology. In other words, in theory, the same circuit implemented in both technologies should take up about 63.2% the area in Intel's technology as it does in TSMC's.
This means that Intel's 14-nanometer technology that is shipping today offers a significant density edge (as measured by the gate pitch by minimum metal pitch metric) over the TSMC 16-nanometer technology that will show up in devices later this year. Further, Intel said at its analyst day in 2013 (and reiterated at the 2014 analyst day) that it would continue to aggressively shrink its technology at the 10-nanometer node.
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I share the opinion of the Bernstein analysts that for Taiwan Semiconductor to match Intel's density at 10-nanometer seems unlikely.
What about performance?
A common way to measure the performance of a particular technology is to look at the saturated drive currents of the NMOS and PMOS transistors. It's my understanding that the higher the current that can be driven through a transistor at a given level of leakage current, the higher performance the transistors.
At the International Electron Devices Meeting, Intel presented a paper showing the NMOS and PMOS saturated drive currents for its 14-nanometer manufacturing technology:
Source: Intel paper. On the left is PMOS; right NMOS
What's interesting is that TSMC published a paper a year prior detailing its 16nm technology. At all of the leakage levels, with both the NMOS and PMOS transistor, at which Intel has provided data, TSMC's 16nm technology offers significantly lower drive currents than Intel's 14nm technology. The Intel technology also operates at a lower voltage than the TSMC 16nm technology detailed (0.7V versus 0.75V).
Now, to TSMC's credit, it has unveiled that it plans to go into mass production of a technology known as 16-nanometer FinFET+. This technology is claimed to improve performance over the 16nm technology by "up to 15%" at the same power level. I still believe that Intel has the higher performing technology, though, at the leakage levels that Intel discussed in its IEDM paper.
The article The Gap Between Intel Corporation and Taiwan Semiconductor Mfg. Co. Ltd. originally appeared on Fool.com.
Ashraf Eassa owns shares of Intel. The Motley Fool recommends Apple and Intel. The Motley Fool owns shares of Apple. Try any of our Foolish newsletter services free for 30 days. We Fools may not all hold the same opinions, but we all believe that considering a diverse range of insights makes us better investors. The Motley Fool has a disclosure policy.
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