At the Intel Developer Forum in Shenzhen, China, the company provided additional details with respect to its 14-nanometer Cherry Trail Atom system-on-chip. Although the company didn't explicitly give out the size of the silicon die itself, the company did give investors a way to calculate that number themselves.
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The die size is important mainly because the cost to manufacture a chip is dependent on the number of chips that can be had from a given silicon wafer. The more chips per wafer, the lower the per-chip cost.
Without further ado, let's figure out the die size of Intel's 14-nanometer Cherry Trail.
Smile for the camera, Cherry Trail!
Here's a picture of the Cherry Trail package, courtesy of a slide deck that Intel showed at its Developer Forum:
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Note that Intel says that the package size is 17 millimeters by 17 millimeters, implying a package size of 289 square millimeters. In order to estimate the size of the actual silicon die (the black rectangle), I measured the dimensions of the package itself, and then measured the dimensions of the die. I then took the ratio of the die measurement to the package size, and multiplied that by 289 square millimeters.
My measurements suggest that the Cherry Trail die has an area of approximately 87 square millimeters. I should caution readers not to view this measurement as precise; but I'm comfortable with the number as a ballpark estimate.
Intel really splurged on the additional features
Intel says that it was able to shrink the CPU cores by 64% in moving from the 22-nanometer Silvermont to the 14-nanometer Airmont. Note that most estimates peg the prior generation Bay Trail chip at more than 100 square millimeters in size.
If Intel had done a straight shrink of Bay Trail, it's likely that the chip would have been somewhere south of 50 square millimeters. However, Intel chose to use the area savings that the 14-nanometer technology brought in order to pack in more functionality.
Exploring the improvements from Bay Trail
With Cherry Trail, Intel quadrupled the number of graphics cores from four to 16. As you can see in the image below, much of Cherry Trail is graphics/media (see the portion inside of the yellow box):
Source: Intel; author annotation.
Intel also integrated a sensor hub, which wasn't present in Bay Trail. The display engine is more robust, with support for higher resolution displays, and more of them -- three instead of two in Bay Trail.
What's next for Intel's mobile chips?
The successor to Cherry Trail is known as Broxton, and it should be built on the same 14-nanometer technology. My expectation is that, because 14-nanometer yields are expected to be mature by the time Broxton ramps, Intel will likely increase the die area of the chip.
The CPU cores should get larger, as Intel will probably need to increase area there to deliver a performance boost from Cherry Trail. Intel is also expected to include more robust media capabilities, such as HEVC video encoding, and increased 3D graphics performance, so that will necessitate an increase in area allocated to graphics/media. The step up probably won't be as large as what we saw in moving from Bay Trail to Cherry Trail, though.
Finally, I believe that Intel will include a significantly enhanced image signal processor -- the one in Cherry Trail doesn't seem to be a big advancement from the one found in Bay Trail/Moorefield -- particularly since Broxton is aimed at high-end phones where camera functionality is important.
The article Intel Corporation Cherry Trail Die Size Revealed originally appeared on Fool.com.
Ashraf Eassa owns shares of Intel. The Motley Fool recommends Intel. Try any of our Foolish newsletter services free for 30 days. We Fools may not all hold the same opinions, but we all believe that considering a diverse range of insights makes us better investors. The Motley Fool has a disclosure policy.
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