Last year, Intel put out a controversial slide at its 2013 investor meeting in which it claimed that its 14-nanometer technology offered a pretty significant density advantage over competing foundries' 14/16-nanometer technologies. In particular, Intel claimed that its 14-nanometer process was approximately 35% denser than Taiwan Semiconductor's 16-nanometer process.
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Now, TSMC took exception to this slide and shortly thereafter published the following slide rebutting Intel's claims:
Source: TSMC via SemiWiki
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TSMC claimed that Intel's 14-nanometer process was only about 15% denser than its own 16-nanometer process and that Intel's 10-nanometer and TSMC's 10-nanometer processes are equally dense. However, with the key density metrics for both processes now known, the question is: Which company was telling the truth?
Looking at it from two angles
Intel's chart was, as we found out this year, based on the metric of gate pitch multiplied by minimum metal pitch (both key determinants of theoretical process density). TSMC's 16-nanometer process offers a gate pitch of 90-nanometers and a minimum metal pitch of 64-nanometers, per its paper at IEDM 2013. Intel's 14-nanometer process offers a 70-nanometer gate pitch and a 52-nanometer minimum metal pitch, according to disclosures by the company.
By Intel's metric, a given logic cell that would take up 3640 square nanometers in the Intel process would require 5760 square nanometers in the TSMC process -- about a 36.8% density edge for Intel. This lines up pretty well with the ~35% density advantage claim that Intel made at its 2013 investor meeting.
Now, if you look at it from the perspective of the smallest published SRAM cell size, the picture changes a bit. According to the ISSCC 2015 program, Intel has achieved a high-density SRAM cell size of 0.05 um^2. TSMC's smallest published 16-nanometer SRAM cell size is 0.07 um^2. Intel's high-density 14-nanometer SRAM cell size represents a 28.5% shrink from TSMC's. Not quite 35%, but it's quite a bit better than the 15% that TSMC claims.
The 16-nanometer claim appears false; hard to believe the 10-nanometer one
Notice in the TSMC slide, the company claims that at the 10-nanometer node, it will completely catch up with Intel. In order for this claim told true, the company will have to pull some pretty serious magic at the 10-nanometer node. Given that Intel has been in the lead for quite some time, it's very difficult to imagine that TSMC will, with Intel investing heavily, simply "catch up."
Indeed, what's really interesting is that at the 16-nanometer node, TSMC was significantly behind both Intel and Samsung in terms of the gate pitch multiplied by metal pitch metric. Samsung, at its 10-nanometer node, claims that it has achieved a 48-nanometer metal pitch and a 64-nanometer gate pitch, implying a density within the same league as Intel's 14-nanometer technology.
Are investors to believe that Taiwan Semiconductor can really make that large of a leap in one generation, particularly given how hard 16nm/16nm FinFET-Plus has been for the company? I don't want to say that it's impossible -- the folks at TSMC may well have pulled it off -- but I seriously doubt it.
The article What's the Verdict on Taiwan Semiconductor Mfg. Co. Ltd.'s Density Claims? originally appeared on Fool.com.
Ashraf Eassa owns shares of Intel. The Motley Fool recommends Intel. The Motley Fool owns shares of Intel. Try any of our Foolish newsletter services free for 30 days. We Fools may not all hold the same opinions, but we all believe that considering a diverse range of insights makes us better investors. The Motley Fool has a disclosure policy.
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